FE Electrical and Computer Digital Systems Practice Problems

The current FE Electrical and Computer specification assigns 8-12 of the 110 exam questions to Digital Systems. Form A contains 9 original problems in this area. The sample below is published in full, with the same worked-solution format used throughout the book.

An 8-bit two's complement adder in a motor controller receives the operands $0101110 1_{2}$ and $0011011 0_{2}$ . The signed decimal value left in the 8-bit result register is:

(A)-109
(B)-108
(C)-19
(D)147

Show worked solution

Answer: (A)

Two positive operands whose true sum exceeds $+ 127$ overflow the format, and the retained pattern $1001001 1_{2}$ reads as -109.

Both words carry a clear sign bit, so each represents a positive quantity, and their true sum climbs past the $+ 127$ ceiling that eight-bit two's complement can hold.

0101110 1_{2} = 64 + 16 + 8 + 4 + 1 = 93

0011011 0_{2} = 32 + 16 + 4 + 2 = 54

93 + 54 = 147 > 127

Column-by-column addition propagates a carry into the sign column but produces no carry out of it, the defining signature of two's complement overflow, so the hardware discards nothing yet stores a pattern that no longer matches the arithmetic sum.

0101110 1_{2} + 0011011 0_{2} = 1001001 1_{2}

C_{in,sign} = 1, C_{out,sign} = 0 \Rightarrow overflow

Read back under the same convention, the leading one carries weight $- 128$ while the remaining set bits contribute 19, so the register reports a negative quantity even though both inputs were positive.

- 128 + 16 + 2 + 1 = - 109

FE Reference Handbook — Electrical and Computer Engineering: Number Systems and Codes, Two's Complement Representation ($N_{\text{signed}} = -b_{n-1}2^{n-1} + \sum_{i=0}^{n-2} b_i 2^i$)

Why the other choices appear

(B)Treating 10010011 as one's complement inverts it to 01101100 = 108 for a reading of -108, one unit short in magnitude because the added one is omitted.
(C)Treating 10010011 as sign-magnitude uses the sign bit plus the 7-bit field 0010011 = 19, giving -19.
(D)Reporting the unsigned value 128 + 16 + 2 + 1 = 147 ignores the sign bit and assumes a register wide enough to avoid overflow.