A processor uses a two-level cache hierarchy. The L1 cache has an access time of 1.0 ns and a miss rate of 6%. An L1 miss is serviced by an L2 cache with an access time of 9 ns and a local miss rate of 25%. An L2 miss is serviced by main memory in 80 ns. The average memory access time seen by the processor is most nearly:
- (A)2.74 ns
- (B)5.80 ns
- (C)6.34 ns
- (D)21.54 ns
Show worked solution
Answer: (A)
Because the 25% L2 miss rate applies only to the 6% of references that already missed in L1, the mean latency is about 2.74 ns.
Multilevel caches compose serially: every reference pays the L1 hit time, and only the fraction that misses reaches the next level.
Quoted for the L2 alone, the 25% miss rate is a local rate and therefore weights only the traffic that reaches L2.
Weighting that 29 ns penalty by the 6% of references that miss in L1 gives the latency averaged over the whole reference stream.
FE Reference Handbook — Computer Systems: Memory Hierarchy, Average Memory Access Time
Why the other choices appear
- (B)Bypassing L2 entirely and charging main memory for every L1 miss: 1.0 + 0.06(80) = 5.80 ns.
- (C)Adding the L2 and main-memory times as parallel penalties both weighted by the L1 miss rate: 1.0 + 0.06(9) + 0.06(80) = 6.34 ns.
- (D)Treating the 25% L2 miss rate as a global rate applied to all references: 1.0 + 0.06(9) + 0.25(80) = 21.54 ns.